1. Field of the Invention
The present invention relates to the field of application specific integrated circuits (ASICs); specifically, it relates to a method for connecting core I/O pins to chip I/O pads and more specifically to backside chip I/O pads.
2. Background of the Invention
With the advance of semiconductor technology, the need for integration to system-on-a-chip (SOC) levels within the ASIC field has increased. While reductions in feature sizes and power supply voltage levels have allowed significant integration improvements, these same integration improvements have made inclusion of complex cores (including analog, mixed signal, memory, and specialty cores) more difficult. For example, certain cores require power supply voltages and/or power consumption levels, which are not compatible with the non-core devices and circuits. Further, while the physical number of interconnection (wiring) levels has increased, the number of physical chip I/Os has become a limiting factor as chip sizes have decreased. Moving from peripheral I/O layout to array I/O layout has also raised new problems. Array I/O allow cores to be positioned anywhere within a chip and designers are placing cores closer to the circuit modules the core supports, raising chip I/O routing and competition issues, power distribution and signal noise issues and modeling and testing issues. These issues impact cost, reliability, design time and overall time to market in a field (ASIC) where cost and time to market are critical concerns.
FIGS. 1 and 2 are exemplary of the physical features and topography of an SOC ASIC utilizing array chip I/O's and containing a core.
FIG. 1 is a partial cross-sectional view of a related art integrated circuit chip. In FIG. 1, integrated circuit chip 100 comprises a silicon substrate 105 on which, a multiplicity of interconnection levels 110 are fabricated. Fabricated between silicon substrate 105 and interconnection levels 110 is a device level 115. Interconnection levels 110 include in order above silicon substrate 115, an M1 level 120, an M2 level 125, an M3 level 130, an M4 level 135, an MT level 140 and a passivation level 145. On top of passivation level 145 are chip I/O pads 150 supporting solder balls 155.
Substrate 105 generally contains the semiconductor portions of devices such as the source, drain, and channels of metal-oxide-silicon (MOS) transistors and device level 115 generally contains the non-semiconductor portions of devices such as the gates of MOS transistors. Each level of interconnection levels 110 includes an insulator, wires formed in the insulator and conductive vias connecting the wires in one level to wires in another level. Interconnect levels 110 wire up devices formed in silicon substrate 105 and device level 115 into circuits and connect those circuits to chip I/O pads 150.
Contained within chip 100, is a core 160. Core 160 includes portions of silicon substrate 105, device level 115, M1 level 120, M2 level 125 and M3 level 130 that are reserved for core devices and circuits. Core 160 is divided into a core circuit portion 165 and a redistribution portion 170. There are no devices in the portions of silicon substrate 105 and device level 115 contained in redistribution portion 170. There is no wiring in portions of M1 level 120 and M2 level 125 contained within redistribution portion 170. A plurality of core I/O pins 175 are located in redistribution portion 170 at M3 level 130. Global wiring in M3 level 130, M4 level 135, MT level 140 and passivation level 145 electrically connect core I/O pins 175 to chip I/O pads 150.
FIG. 2 is a partial plan view of the related art integrated circuit chip of FIG. 1. In FIG. 2, core I/O pins 175 of core 160 are electrically connected to chip I/O pads 150 by global wiring 180. The exact routing of global wiring 180 is determined based upon electrical parameter wiring rules such as line resistance and capacitance, power distribution rules limiting voltage drop and current hot-spots and physical wiring rules such as wire width and length matching. While global wiring may be done by software, designs still need to be simulated (tested) and corrections made multiple times and often by human intervention.
The present invention provides a method to address chip I/O availability in SOC ASIC chips having cores to minimize cost, design time and overall time to market.